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369 lines
13 KiB
Verilog
369 lines
13 KiB
Verilog
/*
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File: axi_master_wr.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module axi_master_wr (/*AUTOARG*/
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// Outputs
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awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot,
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awvalid, wid, wdata, wstrb, wlast, wvalid, bready,
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emesh_wr_wait_inb,
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// Inputs
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aclk, eclk, reset, awready, wready, bid, bresp, bvalid,
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emesh_access_outb, emesh_write_outb, emesh_datamode_outb,
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emesh_ctrlmode_outb, emesh_dstaddr_outb, emesh_srcaddr_outb,
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emesh_data_outb
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);
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parameter MIDW = 6; //ID Width
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parameter MAW = 32; //Address Bus Width
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parameter MDW = 64; //Data Bus Width
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parameter ACH = MAW+2; //Width of all used Write Address Signals
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parameter AFW = 4; //Address channel Fifo address width
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parameter DFW = 4; //Data channel Fifo address width
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parameter DCH = MDW+8; //Width of all used Write Data Signals
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parameter STW = 8; //Number of strobes
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//#########
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//# Inputs
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//#########
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// global signals
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input aclk; // clock source of the axi bus
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input eclk; // clock source of emesh interface
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input reset; // reset
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//########################
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//# Write address channel
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//########################
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input awready; //write address ready
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//########################
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//# Write data channel
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//########################
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input wready; //write ready
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//#########################
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//# Write response channel
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//#########################
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input [MIDW-1:0] bid; //response ID tag
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input [1:0] bresp; //write response
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input bvalid;//write response valid
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//##############################
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//# From the emesh interface
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//##############################
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input emesh_access_outb;
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input emesh_write_outb;
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input [1:0] emesh_datamode_outb;
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input [3:0] emesh_ctrlmode_outb;
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input [31:0] emesh_dstaddr_outb;
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input [31:0] emesh_srcaddr_outb;
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input [31:0] emesh_data_outb;
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//##########
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//# Outputs
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//##########
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//########################
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//# Write address channel
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//########################
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output [MIDW-1:0] awid; //write address ID
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output [MAW-1:0] awaddr; //write address
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output [3:0] awlen; //burst lenght (the number of data transfers)
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output [2:0] awsize; //burst size (the size of each transfer)
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output [1:0] awburst; //burst type
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output [1:0] awlock; //lock type (atomic characteristics)
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output [3:0] awcache; //memory type
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output [2:0] awprot; //protection type
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output awvalid; //write address valid
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//########################
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//# Write data channel
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//########################
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output [MIDW-1:0] wid; //write ID tag (supported only in AXI3)
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output [MDW-1:0] wdata; //write data
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output [STW-1:0] wstrb; //write strobes
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output wlast; //write last, indicates the last transfer in burst
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output wvalid;//write valid
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//########################
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// Write response channel
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//########################
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output bready;//response ready
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//##############################
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//# To the emesh interface
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//##############################
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output emesh_wr_wait_inb;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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//#########
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//# Regs
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//#########
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reg [33:0] addr_reg;
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reg [63:0] data_reg;
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reg emesh_wr_access_reg;
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reg ach_fifo_empty_reg;
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reg [ACH-1:0] ach_fifo_reg;
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reg [63:0] realgn_byte;
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reg [63:0] realgn_hword;
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reg dch_fifo_empty_reg;
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reg [DCH-1:0] dch_fifo_reg;
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reg [7:0] wstrb_hword;
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reg [7:0] wstrb_byte;
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//#########
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//# Wires
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//#########
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wire emesh_wr_access;
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wire [ACH-1:0] ach_fifo_in;
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wire [ACH-1:0] ach_fifo_out;
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wire ach_fifo_wr;
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wire ach_fifo_rd;
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wire ach_fifo_full;
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wire ach_fifo_empty;
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wire ach_advance;
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wire awvalid_awready;
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wire [2:0] realgn_ctrl;
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wire byte_realgn;
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wire hword_realgn;
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wire word_realgn;
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wire [63:0] realgn_word;
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wire [63:0] data_realgn;
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wire [DCH-1:0] dch_fifo_in;
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wire [DCH-1:0] dch_fifo_out;
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wire dch_fifo_wr;
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wire dch_fifo_rd;
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wire dch_fifo_empty;
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wire dch_advance;
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wire wvalid_wready;
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wire [7:0] wstrb_realgn;
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wire [7:0] wstrb_word;
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wire dch_fifo_full;
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//# Incoming transaction should be sampled to prevent timing issues
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assign emesh_wr_wait_inb = ach_fifo_full | dch_fifo_full;
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assign emesh_wr_access = emesh_access_outb & emesh_write_outb &
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~emesh_wr_wait_inb;
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always @ (posedge eclk)
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if (emesh_wr_access)
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addr_reg[33:0] <= {emesh_dstaddr_outb[31:0],emesh_datamode_outb[1:0]};
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always @ (posedge eclk)
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if (emesh_wr_access)
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data_reg[63:0] <= {emesh_srcaddr_outb[31:0],emesh_data_outb[31:0]};
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always @ (posedge eclk or posedge reset)
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if(reset)
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emesh_wr_access_reg <= 1'b0;
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else if(~emesh_wr_wait_inb)
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emesh_wr_access_reg <= emesh_wr_access;
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//#######################################
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//# Address channel synchronization FIFO
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//#######################################
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assign ach_fifo_in[ACH-1:0] = addr_reg[33:0];
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assign ach_fifo_wr = emesh_wr_access_reg & ~emesh_wr_wait_inb;
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assign ach_fifo_rd = ~ach_fifo_empty & (~awvalid | awvalid_awready);
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assign ach_advance = awvalid_awready | ~awvalid;
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/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
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.wr_clk (eclk),
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.wr_data (ach_fifo_in[ACH-1:0]),
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.rd_data (ach_fifo_out[ACH-1:0]),
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.rd_fifo_empty (ach_fifo_empty),
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.wr_fifo_full (ach_fifo_full),
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.wr_write (ach_fifo_wr),
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.rd_read (ach_fifo_rd),
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);
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*/
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fifo #(.DW(ACH), .AW(AFW)) fifo_ach(/*AUTOINST*/
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// Outputs
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.rd_data (ach_fifo_out[ACH-1:0]), // Templated
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.rd_fifo_empty (ach_fifo_empty), // Templated
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.wr_fifo_full (ach_fifo_full), // Templated
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// Inputs
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.reset (reset),
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.wr_clk (eclk), // Templated
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.rd_clk (aclk), // Templated
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.wr_write (ach_fifo_wr), // Templated
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.wr_data (ach_fifo_in[ACH-1:0]), // Templated
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.rd_read (ach_fifo_rd)); // Templated
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//# The data is sampled after exiting FIFO to prevent timing issues
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always @ (posedge aclk or posedge reset)
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if(reset)
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ach_fifo_empty_reg <= 1'b1;
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else if(ach_advance)
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ach_fifo_empty_reg <= ach_fifo_empty;
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always @ (posedge aclk)
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if (ach_advance)
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ach_fifo_reg[ACH-1:0] <= ach_fifo_out[ACH-1:0];
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assign awid[MIDW-1:0] = {(MIDW){1'b0}};
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assign awaddr[MAW-1:0] = ach_fifo_reg[ACH-1:2];
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assign awlen[3:0] = 4'b0000;
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assign awsize[2:0] = {1'b0,ach_fifo_reg[1:0]};
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assign awburst[1:0] = 2'b01;
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assign awlock[1:0] = 2'b00;
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assign awcache[3:0] = 4'b0000;
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assign awprot[2:0] = 3'b000; //unprivileged, secured
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assign awvalid = ~ach_fifo_empty_reg;
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assign awvalid_awready = awvalid & awready;
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//#######################################
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//# Data channel synchronization FIFO
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//#######################################
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assign realgn_ctrl[2:0] = addr_reg[4:2];
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assign byte_realgn = (addr_reg[1:0] == 2'b00);
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assign hword_realgn = (addr_reg[1:0] == 2'b01);
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assign word_realgn = (addr_reg[1:0] == 2'b10);
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always @ (realgn_ctrl[2:0] or data_reg[7:0])
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begin
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casez (realgn_ctrl[2:0])
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3'b000 : realgn_byte[63:0] = {{(56){1'b0}},data_reg[7:0] };
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3'b001 : realgn_byte[63:0] = {{(48){1'b0}},data_reg[7:0],{( 8){1'b0}}};
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3'b010 : realgn_byte[63:0] = {{(40){1'b0}},data_reg[7:0],{(16){1'b0}}};
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3'b011 : realgn_byte[63:0] = {{(32){1'b0}},data_reg[7:0],{(24){1'b0}}};
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3'b100 : realgn_byte[63:0] = {{(24){1'b0}},data_reg[7:0],{(32){1'b0}}};
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3'b101 : realgn_byte[63:0] = {{(16){1'b0}},data_reg[7:0],{(40){1'b0}}};
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3'b110 : realgn_byte[63:0] = {{(8){1'b0}},data_reg[7:0] ,{(48){1'b0}}};
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3'b111 : realgn_byte[63:0] = { data_reg[7:0] ,{(56){1'b0}}};
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default: realgn_byte[63:0] = {{(56){1'b0}},data_reg[7:0]};
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endcase // casez (realgn_ctrl[2:0])
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end // always @ (realgn_ctrl[2:0])
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always @ (realgn_ctrl[2:1] or data_reg[15:0])
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begin
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casez (realgn_ctrl[2:1])
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2'b00 : realgn_hword[63:0] = {{(48){1'b0}},data_reg[15:0]};
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2'b01 : realgn_hword[63:0] = {{(32){1'b0}},data_reg[15:0],{(16){1'b0}}};
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2'b10 : realgn_hword[63:0] = {{(16){1'b0}},data_reg[15:0],{(32){1'b0}}};
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2'b11 : realgn_hword[63:0] = { data_reg[15:0],{(48){1'b0}}};
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default: realgn_hword[63:0] = {{(48){1'b0}},data_reg[15:0]};
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endcase // casez (realgn_ctrl[2:1])
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end
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assign realgn_word[63:0] = realgn_ctrl[2] ? {data_reg[31:0],{(32){1'b0}}} :
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{{(32){1'b0}},data_reg[31:0]};
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assign data_realgn[63:0] = byte_realgn ? realgn_byte[63:0] :
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hword_realgn ? realgn_hword[63:0]:
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word_realgn ? realgn_word[63:0] :
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data_reg[63:0];
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//Write Strobes creation
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always @ (realgn_ctrl[2:0])
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begin
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casez (realgn_ctrl[2:0])
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3'b000 : wstrb_byte[7:0] = 8'b00000001;
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3'b001 : wstrb_byte[7:0] = 8'b00000010;
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3'b010 : wstrb_byte[7:0] = 8'b00000100;
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3'b011 : wstrb_byte[7:0] = 8'b00001000;
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3'b100 : wstrb_byte[7:0] = 8'b00010000;
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3'b101 : wstrb_byte[7:0] = 8'b00100000;
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3'b110 : wstrb_byte[7:0] = 8'b01000000;
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3'b111 : wstrb_byte[7:0] = 8'b10000000;
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default: wstrb_byte[7:0] = 8'b00000001;
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endcase // casez (realgn_ctrl[2:0])
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end // always @ (realgn_ctrl[2:0])
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always @ (realgn_ctrl[2:1])
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begin
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casez (realgn_ctrl[2:1])
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2'b00 : wstrb_hword[7:0] = 8'b00000011;
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2'b01 : wstrb_hword[7:0] = 8'b00001100;
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2'b10 : wstrb_hword[7:0] = 8'b00110000;
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2'b11 : wstrb_hword[7:0] = 8'b11000000;
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default: wstrb_hword[7:0] = 8'b00000011;
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endcase // casez (realgn_ctrl[2:1])
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end
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assign wstrb_word[7:0] = realgn_ctrl[2] ? 8'b11110000 : 8'b00001111;
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assign wstrb_realgn[7:0] = byte_realgn ? wstrb_byte[7:0] :
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hword_realgn ? wstrb_hword[7:0]:
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word_realgn ? wstrb_word[7:0] : {(8){1'b1}};
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assign dch_fifo_in[DCH-1:0] = {data_realgn[63:0],wstrb_realgn[7:0]};
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assign dch_fifo_wr = emesh_wr_access_reg & ~emesh_wr_wait_inb;
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assign dch_fifo_rd = ~dch_fifo_empty & (~wvalid | wvalid_wready);
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assign dch_advance = wvalid_wready | ~wvalid;
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/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
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.wr_clk (eclk),
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.wr_data (dch_fifo_in[DCH-1:0]),
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.rd_data (dch_fifo_out[DCH-1:0]),
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.rd_fifo_empty (dch_fifo_empty),
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.wr_fifo_full (dch_fifo_full),
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.wr_write (dch_fifo_wr),
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.rd_read (dch_fifo_rd),
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);
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*/
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fifo #(.DW(DCH), .AW(DFW)) fifo_dch(/*AUTOINST*/
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// Outputs
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.rd_data (dch_fifo_out[DCH-1:0]), // Templated
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.rd_fifo_empty (dch_fifo_empty), // Templated
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.wr_fifo_full (dch_fifo_full), // Templated
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// Inputs
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.reset (reset),
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.wr_clk (eclk), // Templated
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.rd_clk (aclk), // Templated
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.wr_write (dch_fifo_wr), // Templated
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.wr_data (dch_fifo_in[DCH-1:0]), // Templated
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.rd_read (dch_fifo_rd)); // Templated
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//# The data is sampled after exiting FIFO to prevent timing issues
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always @ (posedge aclk or posedge reset)
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if(reset)
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dch_fifo_empty_reg <= 1'b1;
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else if(dch_advance)
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dch_fifo_empty_reg <= dch_fifo_empty;
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always @ (posedge aclk)
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if (dch_advance)
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dch_fifo_reg[DCH-1:0] <= dch_fifo_out[DCH-1:0];
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assign wid[MIDW-1:0] = {(MIDW){1'b0}};
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assign wdata[MDW-1:0] = dch_fifo_reg[DCH-1:8];
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assign wstrb[STW-1:0] = dch_fifo_reg[7:0];
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assign wlast = 1'b1;
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assign wvalid = ~dch_fifo_empty_reg;
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assign wvalid_wready = wvalid & wready;
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assign bready = 1'b1;
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endmodule // axi_master_wr
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