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60 lines
1.5 KiB
Verilog
60 lines
1.5 KiB
Verilog
/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module fifo_mem (/*AUTOARG*/
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// Outputs
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rd_data,
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// Inputs
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wr_clk, wr_write, wr_data, wr_addr, rd_addr
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);
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parameter DW = 104;
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parameter AW = 2;
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localparam MD = 1<<AW;
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//#########
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//# INPUTS
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//#########
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input wr_clk; //write clock
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input wr_write;
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input [DW-1:0] wr_data;
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input [AW-1:0] wr_addr;
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input [AW-1:0] rd_addr;
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//##########
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//# OUTPUTS
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//##########
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output [DW-1:0] rd_data;
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//########
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//# REGS
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//########
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reg [DW-1:0] mem[MD-1:0];
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//Write
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always @(posedge wr_clk)
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if(wr_write)
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mem[wr_addr[AW-1:0]] <= wr_data[DW-1:0];
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//Read
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assign rd_data[DW-1:0] = mem[rd_addr[AW-1:0]];
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endmodule // fifo_mem
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