parallella-hw/archive/firmware

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This file describes how to reprogram the content of the 128Mb
QSPI boot flash on the Parallella board.

To update the image on a board that has previously been programmed,
power-on the board with no SD card inserted and start with step 9. In
this case no Xilinx USB cable or Xilinx tools are required, only
a serial connection and terminal program.

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Directory Content:

parallella.[7010|7020].flash.bin  (bootable flash image)
parallella.bit.bin	  (FPGA bitstream loaded by U-Boot from SD card)
fsbl.elf 		  (First Stage Boot Loader)
uboot.elf 		  (U-Boot executable)
stub.tcl 		  (tcl script for putting the CPU in debug mode)
ps7_init.tcl 		  (FSBL settings as tcl script for JTAG operation)

The u-boot.elf is compiled from the parallella-uboot repository using the arm
gcc compiler.

The fsbl.elf is generated from the Xilinx tool chain

The parallella fpga bit files are generated by the Xilinx tool chain.

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Pre-requisites:
-Xilinx Platform USB Cable II
-Serial port console cable
-Xilinx tools installed

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1.  Make sure you have xilinx tools installed and you have the 
    correct path set. For example:

    my-machine:~> source /opt/Xilinx/14.7/ISE_DS/settings64.csh

2.  Copy over a raw FPGA bitstream file from the fpga project directory.
    For example: "parallella-hw/fpga/projects/parallella_7020_headless"

3.  Run the Xilinx bootgen utility to create the binary file for the flash,
    An bootgen ".bif" configuration file example is given below.

    the_ROM_image:
    {
    [bootloader]/path/to/fsbl.elf
    /path/to/your/fpga-bitstream.bin
    /path/to/u-boot.elf
   }

   my-machine:~>bootgen -image /path/to/image.bif -o i parallella.XXXX.flash.bin
   
   (where "XXXX" is either 7010 or 7020 to match the Zynq chip on the board)

         
4.  Connect a console cable to the three pin serial port header and a computer.
    running a console application such as putty or tera term.

5.  Connect the Xilinx Platform USB II cable to the JTAG PEC_POWER pins. (Note
    that you will need a PEC_POWER breakout board for this). Connect the
    JTAG cable to the Linux based computer running the Xilinx software. There
    may be a driver conflict between the Xilinx cable and the serial cable so
    the safe bet is to connect the cables in step 2 and 3 to separate computers.

6.  Power on the board

7.  Start the JTAG debugger on machine connected to JTAG cable:

    my-machine:~>xmd

8.  Enter the following command sequence in XMD to run the u-boot application
    through the JTAG loader:

    XMD% connect arm hw
    XMD% source ./ps7_init.tcl
    XMD% ps7_init
    XMD% init_user
    XMD% source ./stub.tcl
    XMD% target 64
    XMD% dow u-boot.elf
    XMD% con

9.  Insert an SD card with the file called "parallella.XXXX.flash.bin" on boot 
    partition, where "XXXX" is either 7010 or 7020 to match the Zynq chip on 
    the board.

10.  In the serial port console program enter the following sequence:
    (Note: Takes several minutes, be patient)

    mmcinfo
    fatload mmc 0 0x4000000 parallella.XXXX.flash.bin
    sf probe 0 0 0
    sf erase 0 0x1000000
    sf write 0x4000000 0 0x$filesize

11.  Set the ethernet address and SKU. The first 6 characters of the MAC address
     contain the Adapteva assigned range of MAC-IDs. The last 6 characters should
     match the serial number ("SN") on the board sticker.  The AdaptevaSKU should
     match the SKU on the sticker including the "SKU" at the start.

    zynq-uboot> set ethaddr 04 4F 8B 00 00 00 (for example)
    zynq-uboot> set AdaptevaSKU SKUA101040    (for example)
    zynq-uboot> saveenv

12. Power down board

13. At this point the board is ready for general use.