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35 lines
1.1 KiB
Plaintext
35 lines
1.1 KiB
Plaintext
***Design Hiearchy***
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parallella_7020_top.v - Top-level FPGA file
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parallella.v - epiphany-Zynq interface
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axi_slave - AXI slave interface for the Zynq
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axi_slave_wr
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axi_slave_addrch
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axi_slave_rd
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axi_slave_addrch
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ax_master - AXI master interface for the Zynq
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axi_master_wr
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axi_master_rd
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ewrapper_link_top - eLink-LVDS wrapper module
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ewrapper_link_receiver
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ewrapper_link_rxi
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ewrapper_io_rx_slow
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ewrapper_link_transmitter
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synchronizer
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ewrapper_link_txo
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io_clock_gen_600mhz
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ewrapper_io_tx_slow
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mux4
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axi_elink_if - AXI<-->eLink interface
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fpgacfg
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pulse2pulse
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parallella_gpio_emio - GPIO pins controlled by PS/EMIO
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system_stub - Zynq processor interface, generated by XPS
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-----------------------
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Revisions:
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4/22/14 FH - Added GPIO module, supporting single-ended or differential IO
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- on either 7010 (24 pins) or 7020 (48 pins).
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