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parallella-hw/archive/fpga/old/hdl
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Andreas Olofsson 046706db8a Reorg
2016-02-03 00:43:14 -05:00
..
elink-gold Reorg 2016-02-03 00:43:14 -05:00
parallella-I Reorg 2016-02-03 00:43:14 -05:00
README.txt Reorg 2016-02-03 00:43:14 -05:00

README.txt 

***Design Hiearchy***

parallella_7020_top.v   - Top-level FPGA file
    parallella.v            - epiphany-Zynq interface
        axi_slave	        - AXI slave interface for the Zynq
            axi_slave_wr
                axi_slave_addrch
            axi_slave_rd
                axi_slave_addrch
        ax_master	        - AXI master interface for the Zynq
            axi_master_wr
            axi_master_rd
        ewrapper_link_top       - eLink-LVDS wrapper module
            ewrapper_link_receiver
                ewrapper_link_rxi
            ewrapper_io_rx_slow
            ewrapper_link_transmitter
                synchronizer
                ewrapper_link_txo
            io_clock_gen_600mhz
            ewrapper_io_tx_slow
                mux4
        axi_elink_if            - AXI<-->eLink interface
            fpgacfg
                pulse2pulse
    parallella_gpio_emio    - GPIO pins controlled by PS/EMIO
    system_stub             - Zynq processor interface, generated by XPS

-----------------------
Revisions:
  4/22/14 FH - Added GPIO module, supporting single-ended or differential IO
             -   on either 7010 (24 pins) or 7020 (48 pins).