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48 lines
1.5 KiB
Verilog
48 lines
1.5 KiB
Verilog
/*
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File: fpga_constants.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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`include "version.v"
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`ifdef TARGET_E16
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`define AXI_COORD 12'h810
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`elsif TARGET_E64
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`define AXI_COORD 12'h820
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`endif
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`define IOSTD_ELINK "LVDS_25"
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`define VIRT_EXT_MEM 4'h8
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`define CHIP_CORE0_ID 12'h808 //core ID of chip's core 0
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`define PHYS_EXT_MEM 4'h3
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`define MM_MMR 4'b1111 //bits 19:16
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`define MM_FPGA 4'b1111 //bits 11:8
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`define REG_SYSCFG 6'h00 //bits 7:2
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`define REG_RESET 6'h01
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`define REG_VERSION 6'h02
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`define REG_FILTERL 6'h03
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`define REG_FILTERH 6'h04
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`define REG_FILTERC 6'h05
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`define REG_TIMEOUT 6'h06
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`define TIMEOUT_DEFAULT 32'h04000000 //Default (1 - 7 sec)
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