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thelio-io-hardware/pcb-thelio-io-sata/thelio-io-sata.kicad_pcb
Darrell Harmon d77276cba4 thelio-io-sata 2.2 
shrink board outline
reduce number of mounting standoffs
use PEM part number
2023-04-13 00:31:48 -04:00

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(kicad_pcb (version 20221018) (generator pcbnew)
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(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
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(gr_text "Prepreg: 7628 or as required for controlled impedance" (at 35 116) (layer "Cmts.User") (tstamp 1d1e27cd-1773-40c8-b196-e751a5f317b9)
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(gr_text "Controlled impedance:\n\nLayer 1 ref layer 2, 100 +- 10% ohm diff: 0.205 mm trace, 0.2032 mm space\nLayer 4 ref layer 3, 100 +- 10% ohm diff: 0.205 mm trace, 0.2032 mm space\n" (at 54 123) (layer "Cmts.User") (tstamp 22d9675b-d412-4190-83ce-e1a4502d6ef4)
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(gr_text "thelio-io-sata_2.2\nBoard must be RoHS compliant\nFabricate to IPC-A-600 Class II\nMaterial: Shengyi S1000-2 or equivalent\nInner copper 1 or 1/2 oz\nOuter copper, min 33.4 um finished\nBlack LPI solder mask over bare copper\nVendor may remove solder mask from via holes, \n maximum of drill size + 3 mil\nFinish: OSP\nSilkscreen: white non conductive\n100% electrical test required\nRemove all unused pads from inner layers\nAll layers positive\nOverall thickness: 1.6 mm +- 10 %\n" (at 28 136) (layer "Cmts.User") (tstamp d5090187-0929-4b9c-99b1-71e799ea0d2f)
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(gr_text "Core: as required for overall thickness" (at 35 112) (layer "Cmts.User") (tstamp f5d0da25-0b8b-43e0-b8f8-bf62a84eacdd)
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