David Cussans 7fe0424ece Getting rid of files that are blocking PR from Pete		2025-03-10 10:55:14 +00:00
..
xxnedtmp/undo1	unfinished changes to power supplies to test merging sch changes in git	2023-02-08 12:47:57 +00:00
xxnedtmp1	Eventually unravelled the chaos of the SFP hierarchy to assign correct power nets to SFP connectors	2023-03-29 15:58:51 +01:00
xxnedtmp2	Pushing files flagged as changed by GIT	2025-02-10 15:19:29 +00:00
xxnedtmp4/undo1	diff pairs to SFPs routed. Somehow Allegro deleted all of the GND planes at some point - I have restored by copying them from an older .brd file	2023-04-05 14:58:48 +01:00
xxnedtmp5/undo1	Modified schematic to rename output busses of DC/DC converter modules. They were both VO<1..0>, which meant they were connected together. Renamed to VO_3V3<1..0> and VO_2V5<1..0> to keep them separate.	2023-03-16 13:17:03 +00:00
xxnedtmp6/undo1	Edited stackup to fit PCBTrain's bog-standard 10 layer stackup. Adjusted diff pair track widths and spacings to get 100R diff impedances on layers Top, 3, 7, 9 & BOTTOM. Saved stackup details because Allegro keeps losing the info if it crashes before you save the .brd file.	2023-03-20 18:36:08 +00:00
xxnedtmp7/undo1	Data In diff pairs all routed. Still needs final tidy up and GND vias adding. Started placing and laying out Clock fanout IC3.	2023-03-23 21:12:04 +00:00
xxnedtmp8/undo1	completed connections to IC6 voltage/current monitor. Redid existing connections to get Kelvin connections to shunt resistors	2023-04-13 11:44:48 +01:00
xxnedtmp12/undo1	heirarchy updated - need to alter names!	2024-07-02 15:13:46 +01:00
08_#20timing.sch_1.mkr	Pushing files flagged as changed by GIT	2025-02-10 15:19:29 +00:00
sessionlog.txt	Replaced (incorrect) yellow side-launch LEDs with one blue one red. Rotated switch SW1. Exported to mtca_interface_board_reocc/top_mib_v3/physical/mib_rev3b_v225.brd	2025-03-10 10:55:12 +00:00