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adw
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new led positions
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2024-08-06 09:57:05 +01:00 |
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archive_libs
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Used new version of Cadence DE-HDL to export to PDF (retaining properties, rather than printing to PS then converting). Moved all components under project ( rather than in ../../../../library and edited cds.lib accordingly
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2025-01-23 13:19:18 +00:00 |
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atcs/led#20red#200603_0
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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Concepthdl.exe346066187
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heirarchy updated - need to alter names!
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2024-07-02 15:13:46 +01:00 |
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Concepthdl.exe1012187968
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diff pairs to SFPs routed. Somehow Allegro deleted all of the GND planes at some point - I have restored by copying them from an older .brd file
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2023-04-05 14:58:48 +01:00 |
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default
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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diode/diode
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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discrete/r
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Mux task remains
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2024-06-21 11:39:15 +01:00 |
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golden_symbols/2#2dpin_jumper/sym_1
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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graphics
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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images0
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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ind/ind
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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mtca_interface_board
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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mtca_interface_board_reocc
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Copied definitive BoM into project. Added some images used for electrical safety review
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2025-01-24 17:38:56 +00:00 |
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ocad_parts_lib
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Edited ATMGA128 part to add TQFP variant
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2023-04-20 21:29:55 +01:00 |
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temp
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J4 pins changed and LED D1/DS1 moved
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2024-09-02 08:09:23 +01:00 |
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testpoint/testpoint
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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tp_demonstrator/led_0
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Adding the cadence files converted by Elgris
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2023-01-05 14:28:39 +00:00 |
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cds.lib
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Used new version of Cadence DE-HDL to export to PDF (retaining properties, rather than printing to PS then converting). Moved all components under project ( rather than in ../../../../library and edited cds.lib accordingly
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2025-01-23 13:19:18 +00:00 |
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front_panel_ethernet_jtag_serial.cpm
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Committing changes - to bve copied to mib_v3
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2024-06-11 12:47:10 +01:00 |
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front_panel_jtag_serial.cpm
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Used new version of Cadence DE-HDL to export to PDF (retaining properties, rather than printing to PS then converting). Moved all components under project ( rather than in ../../../../library and edited cds.lib accordingly
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2025-01-23 13:19:18 +00:00 |
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mib_tongue2.cpm
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Edited tongue2 schematic to include just the tongue-2 uTCA AMC connector ( not both tongue1 and tongue2 )
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2023-02-02 15:12:11 +00:00 |
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timing.cpm
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More hacking with capacitors and resistors. Not yet exporting cleanly to PCB
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2023-01-30 09:28:31 +00:00 |
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top_level_signal_names.txt
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Changed POWER bus to be concatenation of individual signals. Replaced bus-rip with merge. This needs checking! Exported to mib_rev2_v29.brd
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2023-03-08 11:50:10 +00:00 |
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top_mib_v3.cpm
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preparing for quotes
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2024-10-16 13:36:24 +01:00 |
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top.cpm
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Committing changes - to bve copied to mib_v3
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2024-06-11 12:47:10 +01:00 |
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tranz_fpga_module.cpm
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Sorted out physical export issue. Need to add cis_hep_partslib/cis_hep_partslib/Allegro_Library/symbols
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2023-01-30 10:17:59 +00:00 |
