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New Design Review gitified_old_clb_svn/fw/CLBv2_Design/lm32_2nd
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peterj.nikhef.nl 2c7ebd9a93 FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.
2019-07-19 07:26:59 +00:00
..
doc
updated lm32_2nd_pkg device-id definitions (choose random numbers)
2013-07-08 08:11:33 +00:00
ip_cores
Reverted back to revision 306 (from 335 which was edited for adding the TDC)
2013-07-26 09:34:14 +00:00
modules
Watchdog implementation:
2016-08-11 07:57:41 +00:00
sim
Updated ease designs to contain the (hardware) watchdog implementation
2016-08-26 15:48:05 +00:00
syn
Timing violation on RST of TDC frontend fifo's. Removed combinatorial OR. Ran do_xilinx.cmd => new bitfile
2018-10-19 13:12:10 +00:00
top
Added IRQ on illegal (ROM) write access of LM32_2nd DPRAM
2019-05-11 10:32:05 +00:00
lm32_2nd.ews.zip
FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.
2019-07-19 07:26:59 +00:00
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