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Dual-Lane-Feeder-Controller
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Fix Power Supply Vfb #1

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allspice-kyle commented 2022-07-21 17:38:51 +00:00
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This short description prepends any pull request. It is fully markdown compatible. See markdown guide for examples of what you can do!

Resolved Issues

Closes #2

Description

Correct the feedback resistor for IC11. Some additional clean.

Design Review Checklist

Process

  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained

Components

  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power

Schematics

  • Busses
    • UART/USART TX->RX and RX<-TX
    • I2C SDA and SCL pullup with appropriate value per capacitance
    • Setup, hold, access times for data and address busses
  • Analog
    • Sufficient power rails for analog circuits
    • Amplifiers checked for stability
    • Consider signal rate-of-rise and fall for noise radiation
  • General
    • Sufficient bulk capacitance calculated
    • Polarized components checked
    • Electrolytic/tantalum capacitors checked for no reverse voltage
    • Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
    • Sufficient capacitance on low dropout voltage regulators
    • Sufficient time delays and slew rates for comparators
    • Sufficient common mode input voltage rating on opamps
    • Check pin numbers of all custom-generated parts
    • Check reverse base-emitter current/voltage on bipolar transistors
    • Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
    • Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default

PCB

  • Placement
    • Bypass capacitors close to connectors
    • Drivers / receivers close to connectors
    • SMT components on top side, through-hole components on bottom side if possible
  • Mechanical
    • CAD file uploaded
    • Clearance above connectors
    • Clearance below through-hole components
    • Enough space for the minimum bending radius of the wire harness
    • Mounting holes electrically isolated if necessary
      • Mounting holes have via stitching
    • Hole diameters leave margin for plating
    • Board outline defined
    • Mechanical enclosure defined
    • Internal corners are rounded and can be milled
  • Electrical
    • All traces are routed
    • Analog and digital commons joined at only one point
    • ERC passes
    • Isolation barriers are large enough
  • Signal integrity
    • Gaps in ground planes checked and minimized
    • High-speed signals avoid gaps in ground planes
    • Stubs minimized for high-speed signals
    • Option for a shielding can over sensitive circuitry e.g. RF?
  • Copper pour
    • All planes have been poured
    • Planes and pours checked for high-impedance paths
    • No pour between adjacent pins on ICs
  • Traces
    • Trace-pad connections sufficiently obtuse (angle 90 deg or more)
    • Trace widths sufficient for the current draw and max heating
    • No connections between adjacent pins on ICs
    • Vias for internal power traces sufficiently large
    • Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
  • Thermal
    • Temperature sensitive components placed away from hot components
    • Thermal vias in thermal pads
  • Testing
    • Test points on PCBs for critical circuits, hard to reach nets
    • Ground connection points close to analog test points
  • Silk screen
    • Notes and documentation
      • Updated revision number
      • Updated date
      • Blank space designated for a serial / assembly number
    • No silk screen over pads / vias
    • Text is readable from at most two directions
    • Silk screen size / font will legible after printing
    • Connector pin-outs labeled
    • Fuse size and type marked on PCB
*This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!* ## Resolved Issues Closes #2 ## Description Correct the feedback resistor for `IC11`. Some additional clean. ## Design Review Checklist ### Process - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [ ] Update relevant system architecture documents - [ ] Update project README page - [ ] Simulations uploaded and outputs explained ### Components - [ ] Unpopulated components are denoted DNI - [ ] Components meet environmental specifications - [ ] All components have quantity, reference designator and description - [ ] Suggested and alternate manufacturers listed - [ ] Price and stock checked for each component - [ ] Component derating - [ ] Voltage - [ ] Current - [ ] Power at worst-case operating temperature - [ ] Temperature at worst-case power ### Schematics - [ ] Busses - [ ] UART/USART TX->RX and RX<-TX - [ ] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Setup, hold, access times for data and address busses - [ ] Analog - [ ] Sufficient power rails for analog circuits - [ ] Amplifiers checked for stability - [ ] Consider signal rate-of-rise and fall for noise radiation - [ ] General - [ ] Sufficient bulk capacitance calculated - [ ] Polarized components checked - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF - [ ] Sufficient capacitance on low dropout voltage regulators - [ ] Sufficient time delays and slew rates for comparators - [ ] Sufficient common mode input voltage rating on opamps - [ ] Check pin numbers of all custom-generated parts - [ ] Check reverse base-emitter current/voltage on bipolar transistors - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default ### PCB - [ ] Placement - [ ] Bypass capacitors close to connectors - [ ] Drivers / receivers close to connectors - [ ] SMT components on top side, through-hole components on bottom side if possible - [ ] Mechanical - [ ] CAD file uploaded - [ ] Clearance above connectors - [ ] Clearance below through-hole components - [ ] Enough space for the minimum bending radius of the wire harness - [ ] Mounting holes electrically isolated if necessary - [ ] Mounting holes have via stitching - [ ] Hole diameters leave margin for plating - [ ] Board outline defined - [ ] Mechanical enclosure defined - [ ] Internal corners are rounded and can be milled - [ ] Electrical - [ ] All traces are routed - [ ] Analog and digital commons joined at only one point - [ ] ERC passes - [ ] Isolation barriers are large enough - [ ] Signal integrity - [ ] Gaps in ground planes checked and minimized - [ ] High-speed signals avoid gaps in ground planes - [ ] Stubs minimized for high-speed signals - [ ] Option for a shielding can over sensitive circuitry e.g. RF? - [ ] Copper pour - [ ] All planes have been poured - [ ] Planes and pours checked for high-impedance paths - [ ] No pour between adjacent pins on ICs - [ ] Traces - [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more) - [ ] Trace widths sufficient for the current draw and max heating - [ ] No connections between adjacent pins on ICs - [ ] Vias for internal power traces sufficiently large - [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces - [ ] Thermal - [ ] Temperature sensitive components placed away from hot components - [ ] Thermal vias in thermal pads - [ ] Testing - [ ] Test points on PCBs for critical circuits, hard to reach nets - [ ] Ground connection points close to analog test points - [ ] Silk screen - [ ] Notes and documentation - [ ] Updated revision number - [ ] Updated date - [ ] Blank space designated for a serial / assembly number - [ ] No silk screen over pads / vias - [ ] Text is readable from at most two directions - [ ] Silk screen size / font will legible after printing - [ ] Connector pin-outs labeled - [ ] Fuse size and type marked on PCB <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
allspice-kyle added 2 commits 2022-07-21 17:38:51 +00:00
allspice-kyle requested review from mark-hughes 2022-07-21 18:08:10 +00:00
allspice-kyle reviewed 2022-07-21 18:12:07 +00:00
Feeder Board.PcbDoc
allspice-kyle commented 2022-07-21 18:12:06 +00:00
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@mark-hughes did this EOL connector get reviewed?

!thumbnail[](Feeder Board.PcbDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" layers="82,74,72,71,69,65,56,33,1,32,34" diff-visibility="full" variant="default" view-coords="5.3,0.5,12.2,26.5" aspect-ratio="6.817" } @mark-hughes did this EOL connector get reviewed?
allspice-kyle reviewed 2022-07-21 18:27:30 +00:00
Power Supply.SchDoc
allspice-kyle commented 2022-07-21 18:27:30 +00:00
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Can we update this with a comment/note for what feedback values we chose.

!thumbnail[](Power Supply.SchDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" diff-visibility="full" variant="default" view-coords="67.5,24.5,72.1,29.2" aspect-ratio="1.282" } Can we update this with a comment/note for what feedback values we chose.
mark-hughes requested changes 2022-07-21 18:30:50 +00:00
mark-hughes left a comment
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Kyle, Mark's layout is absolutely adorable. I love watching new designers learn how to do things the right way and Mark has so much to learn.

Kyle, Mark's layout is absolutely adorable. I love watching new designers learn how to do things the right way and Mark has so much to learn.
Feeder Board.PcbDoc
mark-hughes commented 2022-07-21 18:16:40 +00:00
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Remember to check for shorts.

!thumbnail[](Feeder Board.PcbDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" layers="1" diff-visibility="none" variant="default" view-coords="10.2,47.1,12.3,58.0" aspect-ratio="6.817" } Remember to check for shorts.
Feeder Board.PcbDoc
mark-hughes commented 2022-07-21 18:18:11 +00:00
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This will cause solder wicking. Check out IPC-7351?

!thumbnail[](Feeder Board.PcbDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" layers="82,1" diff-visibility="none" variant="default" view-coords="25.0,67.1,27.2,82.4" aspect-ratio="6.817" } This will cause solder wicking. Check out IPC-7351?
Feeder Board.PcbDoc
mark-hughes commented 2022-07-21 18:12:43 +00:00
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Double check the land pattern here -- looks like some trace stubs on the land pattern.

!thumbnail[](Feeder Board.PcbDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" layers="82,74,72,71,69,65,56,33,1,32,34" diff-visibility="full" variant="default" view-coords="42.8,31.4,45.7,48.1" aspect-ratio="6.817" } Double check the land pattern here -- looks like some trace stubs on the land pattern.
Feeder Board.PcbDoc
mark-hughes commented 2022-07-21 18:23:13 +00:00
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Check courtyard

!thumbnail[](Feeder Board.PcbDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" layers="71" diff-visibility="none" variant="default" view-coords="45.5,36.2,53.5,61.6" aspect-ratio="6.817" } Check courtyard
allspice-kyle commented 2022-07-21 18:32:19 +00:00
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All set. They are correct.

All set. They are correct.
allspice-kyle marked this conversation as resolved
Feeder Board.PcbDoc
mark-hughes commented 2022-07-21 18:20:57 +00:00
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Not a problem at all.

!thumbnail[](Feeder Board.PcbDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" layers="82,1" diff-visibility="none" variant="default" view-coords="46.4,73.3,59.3,94.3" aspect-ratio="6.817" } Not a problem at all.
Feeder Board.PcbDoc
mark-hughes commented 2022-07-21 18:20:29 +00:00
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IPC-7351!

!thumbnail[](Feeder Board.PcbDoc){ diff="kyle/Dual-Lane-Feeder-Controller:c7daa5edbd01ca422c204fdf94d4f87e01895f71...410e2990466b4d01bafe371cc990717296bd1908" pr="1" layers="82,1" diff-visibility="none" variant="default" view-coords="50.3,13.1,54.8,34.7" aspect-ratio="6.817" } IPC-7351!
allspice-kyle added 1 commit 2022-07-21 18:48:41 +00:00
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