AllSpice-Demos/OrCAD-Demo
AllSpice-Demos/OrCAD-Demo
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Fix schematic and PCB errors #1

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AllSpiceAlice wants to merge 8 commits from develop into main
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merge into: AllSpice-Demos:main
Conversation 5 Commits 8 Files Changed 2 +503 -783
6 changed files with 503 additions and 783 deletions
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RPI-PICO-R3a-PUBLIC.brd
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MikaChanical commented 2024-08-06 05:40:24 +00:00
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@AllSpiceAlice, mechanical review complete. No change to board outline, or mounting features. All new components (and old components) are below the height limit. It think it's ready!

@AllSpiceAlice, mechanical review complete. No change to board outline, or mounting features. All new components (and old components) are below the height limit. It think it's ready! !thumbnail[](RPI-PICO-R3a-PUBLIC.brd){ diff="AllSpice-Demos/OrCAD-Demo:ad10cfced55b1abdba8d8a1c924de5d19d891bd7...d815fc8d16966b6c4b65eb4b0f26d05d4212cde7" pr="1" layers="81,82,1,32,116,115,111,67,66,42,41,65,64,40,37,38,35,36,110,109,108,107,33,34,58,57,106,105,104,103" diff-visibility="full" variant="default" view-coords="2.3,1.3,96.9,99.0" aspect-ratio="0.510" }
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daniel commented 2024-08-06 05:46:35 +00:00
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Thank you for removing the alternate crystal footprint.

!thumbnail[](RPI-PICO-R3a-PUBLIC.brd){ diff="AllSpice-Demos/OrCAD-Demo:ad10cfced55b1abdba8d8a1c924de5d19d891bd7...d815fc8d16966b6c4b65eb4b0f26d05d4212cde7" pr="1" layers="81,82,1,32,116,115,111,67,66,42,41,65,64,40,37,38,35,36,110,109,108,107,33,34,58,57,106,105,104,103" diff-visibility="full" variant="default" view-coords="28.3,61.1,63.9,74.4" aspect-ratio="0.510" } Thank you for removing the alternate crystal footprint.
MikaChanical commented 2024-10-17 00:17:28 +00:00
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@AllSpiceAlice , the spec for the mounting holes is 2.1mm (± 0.05mm). We're getting reports that the prototypes aren't hitting this spec. Can you check the actual file?

!thumbnail[](RPI-PICO-R3a-PUBLIC.brd){ diff="AllSpice-Demos/OrCAD-Demo:ad10cfced55b1abdba8d8a1c924de5d19d891bd7...d815fc8d16966b6c4b65eb4b0f26d05d4212cde7" pr="1" layers="81,82,1,32,67,66,42,41,65,64,40,37,38,35,36,33,34,57" diff-visibility="full" variant="default" view-coords="23.5,7.0,80.3,17.8" aspect-ratio="0.510" } @AllSpiceAlice , the spec for the mounting holes is 2.1mm (± 0.05mm). We're getting reports that the prototypes aren't hitting this spec. Can you check the actual file?
gautam commented 2024-10-25 16:27:05 +00:00
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@daniel Hey do we really need 10mil trace here?

!thumbnail[](RPI-PICO-R3a-PUBLIC.brd){ diff="AllSpice-Demos/OrCAD-Demo:ad10cfced55b1abdba8d8a1c924de5d19d891bd7...b0d764f6a36b18d467021a4ffdd30a93ac150476" pr="1" layers="81,82,1,32,67,66,42,41,65,64,40,37,38,35,36,33,34,57" diff-visibility="full" variant="default" view-coords="13.0,12.5,58.6,27.7" aspect-ratio="0.510" } @daniel Hey do we really need 10mil trace here?

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allegro.jrl
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\t (00:00:01) allegro 24.1 P001 (4234998) [9/4/2024] Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Wed Oct 16 19:21:30 2024
\t (00:00:01) Host=FLOORPUTER User=danie Pid=323424 CPUs=20
\t (00:00:01) CmdLine= c:\cadence\orcadx_24.1\tools\bin\allegro.exe C:\Users\danie\Documents\git-repos\OrCAD-Demo\RPI-PICO-R3a-PUBLIC.brd
\t (00:00:01)
\t (00:00:01) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:07) fillin yes
\i (00:00:07) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "RPI-PICO-R3a-PUBLIC"
\d (00:00:07) Design opened: C:/Users/danie/Documents/git-repos/OrCAD-Demo/RPI-PICO-R3a-PUBLIC.brd
\i (00:00:07) trapsize 25729
\i (00:00:07) trapsize 27372
\i (00:00:07) trapsize 25729
\i (00:00:07) trapsize 19305
\i (00:00:07) trapsize 19305
\i (00:00:07) generaledit
\t (00:00:22) last pick: 193.5328 -52.0270
\w (00:00:22) WARNING(SPMHUT-40): Pick is outside the extent of the drawing ... pick again.
\i (00:00:26) zoom out 1
\i (00:00:26) setwindow pcb
\i (00:00:26) zoom out -4.5367 42.9537
\i (00:00:26) trapsize 19305
\i (00:00:27) zoom out 1
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out -4.5367 42.9537
\i (00:00:27) trapsize 19305
\i (00:00:27) zoom out 1
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out -4.5367 43.3398
\i (00:00:27) trapsize 19305
\i (00:00:27) zoom out 1
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out -4.5367 43.3398
\i (00:00:27) trapsize 19305
\i (00:00:27) zoom out 1
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out -4.5367 43.3398
\i (00:00:27) trapsize 19305
\i (00:00:27) zoom out 1
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out -4.5367 43.3398
\i (00:00:27) trapsize 19305
\i (00:00:27) zoom out 1
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out -4.5367 43.3398
\i (00:00:27) trapsize 19305
\i (00:00:27) pick grid -4.5367 43.7259
\t (00:00:27) last pick: -4.5500 43.7500
\i (00:00:28) zoom in 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom in 5.1158 47.9730
\i (00:00:28) trapsize 9653
\i (00:00:28) zoom out 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom out 5.1158 47.9731
\i (00:00:28) trapsize 19305
\i (00:00:28) zoom out 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom out 5.1158 47.9730
\i (00:00:28) trapsize 19305
\i (00:00:28) zoom out 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom out 5.1158 47.9730
\i (00:00:28) trapsize 19305
\i (00:00:28) zoom out 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom out 5.1158 47.9730
\i (00:00:28) trapsize 19305
\i (00:00:28) zoom out 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom out 5.1158 47.9730
\i (00:00:28) trapsize 19305
\i (00:00:28) zoom out 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom out 5.1158 47.9730
\i (00:00:28) trapsize 19305
\i (00:00:28) zoom in 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom in 5.1158 47.9730
\i (00:00:28) trapsize 9653
\i (00:00:28) zoom in 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom in 5.1158 47.9731
\i (00:00:28) trapsize 4826
\i (00:00:28) zoom in 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom in 5.1159 47.9731
\i (00:00:28) trapsize 2413
\i (00:00:28) zoom in 1
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom in 5.1159 47.9731
\i (00:00:28) trapsize 1207
\i (00:00:29) zoom in 1
\i (00:00:29) setwindow pcb
\i (00:00:29) zoom in 5.1159 47.9731
\i (00:00:29) trapsize 603
\i (00:00:29) zoom in 1
\i (00:00:29) setwindow pcb
\i (00:00:29) zoom in 5.1159 47.9610
\i (00:00:29) trapsize 302
\i (00:00:29) zoom out 1
\i (00:00:29) setwindow pcb
\i (00:00:29) zoom out 5.1159 47.9611
\i (00:00:29) trapsize 603
\i (00:00:30) zoom out 1
\i (00:00:30) setwindow pcb
\i (00:00:30) zoom out 5.1158 47.9610
\i (00:00:30) trapsize 1207
\i (00:00:31) pick grid 5.3331 49.1918
\t (00:00:31) last pick: 5.3500 49.2000
\i (00:00:32) pick grid 5.3331 49.1918
\t (00:00:32) last pick: 5.3500 49.2000
\i (00:00:32) pick grid dbl 5.3331 49.1918
\t (00:00:32) last pick: 5.3500 49.2000
\i (00:00:33) pick grid 5.1642 50.4225
\t (00:00:33) last pick: 5.1500 50.4000
\i (00:00:36) setwindow form.find
\i (00:00:36) FORM find all_on
\i (00:00:37) set

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allegro.jrl,1
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batch_drc.log
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(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : RPI-PICO-R3a-PUBLIC.brd )
( Software Version : 24.1P001 )
( Date/Time : Wed Oct 16 19:23:33 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 135
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

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master.tag
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RPI-PICO-R3a-PUBLIC.brd

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padstack_editor.jrl
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\t (00:00:00) padstack_editor 24.1 P001 (4234998) [9/4/2024] Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Wed Oct 16 19:18:34 2024
\t (00:00:00) Host=FLOORPUTER User=danie Pid=323412 CPUs=20
\t (00:00:00) CmdLine= padstack_editor -mpssession danie -file C:/Users/danie/AppData/Local/Temp/#Taaaaak95596.tmp -pname C50_H210M360N -data C:/Users/danie/AppData/Local/Temp/#Taaaaan95596.tmp
\t (00:00:00)
\d (00:00:11) QtSignal GuidedTabsParent GuidedTabs currentChanged Drill
\d (00:00:25) QtSignal GuidedTabsParent GuidedDrillTab keyPressEvent 16777237 0 false 1
\d (00:00:27) QtSignal GuidedDrillTab HolePlusTolerance editingFinished "0.0500"
\d (00:00:46) QtSignal MainWindow Save triggered
\d (00:00:46) QtSignal GuidedDrillTab HoleMinusTolerance editingFinished "0.0500"
\d (00:00:55) QtSignal MainWindow pseCheckBrowser closed
\d (00:01:02) QtSignal MainWindow Open triggered
\d (00:01:04) QtFillin Cancel
\d (00:01:05) QtSignal MainWindow Save triggered
\d (00:01:08) QtSignal MainWindow pseCheckBrowser closed
\d (00:01:20) QtSignal MainWindow Exit triggered
\d (00:01:22) QtFillin Yes
\d (00:01:24) QtSignal MainWindow pseCheckBrowser closed
\t (00:01:24) Journal end - Wed Oct 16 19:19:59 2024