11 lines
271 B
VHDL
11 lines
271 B
VHDL
-- generated by newgenasym Fri Oct 24 13:54:31 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity csmd0805 is
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port (
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A: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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B: OUT STD_LOGIC_VECTOR (0 DOWNTO 0));
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end csmd0805;
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