Tubii_Tk2/Parts/parts/capacitors/tant0805/entity/verilog.v~
2015-02-27 19:09:38 -05:00

14 lines
169 B
Coq

// generated by newgenasym Mon Sep 13 13:16:51 2010
module csmd0805 (a, b);
input [0:0] a;
output [0:0] b;
initial
begin
end
endmodule