11 lines
227 B
VHDL
11 lines
227 B
VHDL
-- generated by newgenasym Tue Apr 5 18:47:15 2011
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mur105 is
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port (
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AN: INOUT STD_LOGIC;
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CAT: INOUT STD_LOGIC);
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end mur105;
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