15 lines
369 B
VHDL
15 lines
369 B
VHDL
-- generated by newgenasym Fri Apr 08 09:47:45 2011
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \100e101\ is
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port (
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D0: IN STD_LOGIC;
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D1: IN STD_LOGIC;
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D2: IN STD_LOGIC;
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D3: IN STD_LOGIC;
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Q: OUT STD_LOGIC;
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\q*\: OUT STD_LOGIC);
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end \100e101\;
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