Tubii_Tk2/Parts/parts/ecl/100el34/entity/verilog.v
2015-02-27 19:09:38 -05:00

25 lines
415 B
Verilog

// generated by newgenasym Wed Jul 16 15:49:22 2014
module \100el34 (clk, \clk* , \en* , mr, nc, out2, \out2* , out4, \out4* , out8, \out8* ,
vbb);
input clk;
input \clk* ;
input \en* ;
input mr;
inout nc;
output out2;
output \out2* ;
output out4;
output \out4* ;
output out8;
output \out8* ;
input vbb;
initial
begin
end
endmodule