21 lines
573 B
VHDL
21 lines
573 B
VHDL
-- generated by newgenasym Wed Jul 16 15:49:22 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \100el34\ is
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port (
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CLK: IN STD_LOGIC;
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\clk*\: IN STD_LOGIC;
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\en*\: IN STD_LOGIC;
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MR: IN STD_LOGIC;
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NC: INOUT STD_LOGIC;
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OUT2: OUT STD_LOGIC;
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\out2*\: OUT STD_LOGIC;
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OUT4: OUT STD_LOGIC;
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\out4*\: OUT STD_LOGIC;
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OUT8: OUT STD_LOGIC;
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\out8*\: OUT STD_LOGIC;
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VBB: IN STD_LOGIC);
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end \100el34\;
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