20 lines
302 B
Verilog
20 lines
302 B
Verilog
// generated by newgenasym Mon Oct 4 14:19:14 2010
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module \10e016 (\ce* , clk, mr, p, \pe* , q, \tc* , tcld);
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input \ce* ;
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input clk;
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input mr;
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input [7:0] p;
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input \pe* ;
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output [7:0] q;
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output \tc* ;
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input tcld;
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initial
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begin
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end
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endmodule
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