17 lines
475 B
VHDL
17 lines
475 B
VHDL
-- generated by newgenasym Mon Oct 4 14:19:14 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \10e016\ is
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port (
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\ce*\: IN STD_LOGIC;
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CLK: IN STD_LOGIC;
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MR: IN STD_LOGIC;
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P: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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\pe*\: IN STD_LOGIC;
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Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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\tc*\: OUT STD_LOGIC;
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TCLD: IN STD_LOGIC);
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end \10e016\;
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