45 lines
1.6 KiB
Verilog
45 lines
1.6 KiB
Verilog
// generated by chdl_uprev Thu Sep 4 17:25:24 1997
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`timescale 1ns/100ps
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module \10e016 (\ce* , clk, mr, p, \pe* , q, \tc* , tcld);
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input [7:0] p;
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input tcld;
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input \ce* ;
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input clk;
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input \pe* ;
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input mr;
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output [7:0] q;
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output \tc* ;
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MC10E016 inst1 (/*.vee(unconnected)*/,
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/*.NC(unconnected)*/,
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/*.P0*/ p[0],
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/*.P1*/ p[1],
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/*.P2*/ p[2],
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/*.P3*/ p[3],
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/*.P4*/ p[4],
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/*.gnd2(unconnected)*/,
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/*.Q0*/ q[0],
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/*.Q1*/ q[1],
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/*.Q2*/ q[2],
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/*.Q3*/ q[3],
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/*.Q4*/ q[4],
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/*.gnd2(unconnected)*/,
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/*.Q5*/ q[5],
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/*.gnd1(unconnected)*/,
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/*.Q6*/ q[6],
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/*.Q7*/ q[7],
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/*.TC_*/ \tc* ,
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/*.gnd2(unconnected)*/,
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/*.P5*/ p[5],
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/*.P6*/ p[6],
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/*.P7*/ p[7],
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/*.CE_*/ \ce* ,
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/*.PE_*/ \pe* ,
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/*.MR*/ mr,
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/*.CLK*/ clk,
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/*.TCLD*/ tcld );
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endmodule
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