19 lines
321 B
Verilog
19 lines
321 B
Verilog
// generated by newgenasym Tue May 18 12:05:22 2010
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module \10e101 (a, b, c, d, y, \y* );
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parameter size = 1;
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input [size-1:0] a;
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input [size-1:0] b;
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input [size-1:0] c;
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input [size-1:0] d;
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output [size-1:0] y;
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output [size-1:0] \y* ;
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initial
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begin
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end
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endmodule
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