18 lines
572 B
VHDL
18 lines
572 B
VHDL
-- generated by newgenasym Tue May 18 12:05:22 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \10e101\ is
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generic (
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size:positive:= 1
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);
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port (
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A: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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B: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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C: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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D: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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Y: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\y*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
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end \10e101\;
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