21 lines
562 B
Verilog
21 lines
562 B
Verilog
// generated by genview Fri Jan 16 22:43:15 1998
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`timescale 1ns/100ps
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module \10e101 (a, b, c, d, y, \y* );
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parameter size = 1;
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input [size-1:0] a;
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input [size-1:0] b;
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input [size-1:0] c;
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input [size-1:0] d;
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output [size-1:0] y;
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output [size-1:0] \y* ;
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MC10E101P inst1[size-1:0] (/*.D0D*/ d,
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/*.D0C*/ c,
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/*.D0B*/ b,
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/*.D0A*/ a,
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/*.Q0*/ y,
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/*.Q0_*/ \y* );
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endmodule |