36 lines
841 B
Verilog
36 lines
841 B
Verilog
// generated by newgenasym Fri Jul 30 19:05:30 2010
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module \10e104 (a0, a1, a2, a3, a4, b0, b1, b2, b3, b4, f, \f* , y0, \y0* , y1, \y1* , y2,
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\y2* , y3, \y3* , y4, \y4* );
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parameter size = 1;
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input [size-1:0] a0;
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input [size-1:0] a1;
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input [size-1:0] a2;
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input [size-1:0] a3;
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input [size-1:0] a4;
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input [size-1:0] b0;
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input [size-1:0] b1;
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input [size-1:0] b2;
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input [size-1:0] b3;
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input [size-1:0] b4;
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output [size-1:0] f;
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output [size-1:0] \f* ;
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output [size-1:0] y0;
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output [size-1:0] \y0* ;
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output [size-1:0] y1;
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output [size-1:0] \y1* ;
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output [size-1:0] y2;
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output [size-1:0] \y2* ;
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output [size-1:0] y3;
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output [size-1:0] \y3* ;
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output [size-1:0] y4;
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output [size-1:0] \y4* ;
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initial
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begin
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end
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endmodule
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