34 lines
1.5 KiB
VHDL
34 lines
1.5 KiB
VHDL
-- generated by newgenasym Fri Jul 30 19:05:30 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \10e104\ is
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generic (
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size:positive:= 1
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);
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port (
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A0: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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A1: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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A2: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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A3: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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A4: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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B0: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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B1: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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B2: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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B3: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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B4: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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F: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\f*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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Y0: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\y0*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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Y1: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\y1*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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Y2: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\y2*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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Y3: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\y3*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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Y4: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\y4*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
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end \10e104\;
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