22 lines
575 B
Verilog
22 lines
575 B
Verilog
// generated by genview Fri Jan 16 22:43:51 1998
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`timescale 1ns/100ps
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module \10e116 (a, \b* , ref, y, \y* );
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parameter size = 1;
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parameter VBBD0 = "VBBD0";
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parameter VBBD0_ = "VBBD0_";
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input [size-1:0] a;
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input [size-1:0] \b* ;
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output [size-1:0] y;
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output ref;
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output [size-1:0] \y* ;
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MC10E116P #(VBBD0, VBBD0_) inst1[size-1:0] (/*.VBB*/ ref,
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/*.D0*/ a,
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/*.D0_*/ \b* ,
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/*.Q0*/ y,
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/*.Q0_*/ \y* );
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endmodule
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