45 lines
1.5 KiB
Verilog
45 lines
1.5 KiB
Verilog
// generated by chdl_uprev Thu Sep 4 17:21:57 1997
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`timescale 1ns/100ps
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module \10e131 (clk, d, en, q, \q* , r, s);
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parameter size = 1;
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input s;
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input [size-1:0] d;
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input clk;
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input en;
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input r;
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output [size-1:0] q;
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output [size-1:0] \q* ;
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MC10E131 inst1 (/*.vee(unconnected)*/,
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/*.CC*/ clk,
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/*.S03*/ s,
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/*.D0*/ d,
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/*.CE0_*/ en ,
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/*.R0*/ r,
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/*.D1*/ ,
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/*.CE1_*/ ,
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/*.R1*/ ,
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/*.nc10(unconnected)*/,
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/*.gnd2(unconnected)*/,
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/*.Q0*/ q,
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/*.Q0_*/ \q* ,
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/*.Q1*/ ,
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/*.Q1_*/ ,
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/*.gnd1(unconnected)*/,
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/*.Q2*/ ,
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/*.Q2_*/ ,
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/*.Q3*/ ,
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/*.Q3_*/ ,
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/*.gnd2(unconnected)*/,
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/*.R2*/ ,
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/*.CE2_*/ ,
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/*.D2*/ ,
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/*.R3*/ ,
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/*.CE3_*/ ,
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/*.D3*/ ,
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/*.S12*/ );
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endmodule
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