12 lines
267 B
VHDL
12 lines
267 B
VHDL
-- generated by newgenasym Mon Aug 30 14:52:10 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \10elt24\ is
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port (
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D: IN STD_LOGIC;
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Q: OUT STD_LOGIC;
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\q*\: OUT STD_LOGIC);
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end \10elt24\;
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