23 lines
387 B
Verilog
23 lines
387 B
Verilog
// generated by newgenasym Mon Aug 2 14:26:26 2010
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module \10ep142 (clk0, \clk0* , clk1, \clk1* , d, mr, q, \q7* , \s-in , \s-in* , sel);
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input clk0;
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input \clk0* ;
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input clk1;
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input \clk1* ;
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input [8:0] d;
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input mr;
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output [8:0] q;
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output \q7* ;
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input \s-in ;
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input \s-in* ;
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input sel;
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initial
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begin
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end
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endmodule
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