20 lines
579 B
VHDL
20 lines
579 B
VHDL
-- generated by newgenasym Mon Aug 2 14:26:26 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \10ep142\ is
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port (
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CLK0: IN STD_LOGIC;
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\clk0*\: IN STD_LOGIC;
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CLK1: IN STD_LOGIC;
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\clk1*\: IN STD_LOGIC;
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D: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
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MR: IN STD_LOGIC;
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Q: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
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\q7*\: OUT STD_LOGIC;
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\s-in\: IN STD_LOGIC;
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\s-in*\: IN STD_LOGIC;
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SEL: IN STD_LOGIC);
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end \10ep142\;
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