16 lines
202 B
Verilog
16 lines
202 B
Verilog
// generated by newgenasym Wed Oct 29 13:44:37 2014
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module \10ep90 (d, \d* , q, \q* );
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input d;
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input \d* ;
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output q;
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output \q* ;
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initial
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begin
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end
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endmodule
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