Tubii_Tk2/Parts/parts/ecl/10h103/entity/vhdl.vhd
2015-02-27 19:09:38 -05:00

12 lines
265 B
VHDL

-- generated by newgenasym Fri Jan 23 17:38:19 2015
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \10h103\ is
port (
D1: IN STD_LOGIC;
D2: IN STD_LOGIC;
Q: OUT STD_LOGIC);
end \10h103\;