12 lines
265 B
VHDL
12 lines
265 B
VHDL
-- generated by newgenasym Fri Jan 23 17:38:19 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \10h103\ is
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port (
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D1: IN STD_LOGIC;
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D2: IN STD_LOGIC;
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Q: OUT STD_LOGIC);
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end \10h103\;
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