Tubii_Tk2/Parts/parts/ecl/10h116/swift_map/verilog.map
2015-02-27 19:09:38 -05:00

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FILE_TYPE=VERILOG_MAP;
PRIMITIVE '10H116';
DEFAULT_MODEL=ECL16;
UPPER_CASE=TRUE;
MODEL 'ECL16';
PROPERTY
PORT_ORDER = '(AIN,AINN,AOUT,AOUTN)';
COMPONENT='MC10H116';
RANGE;
MEMORYFILE;
END_PROPERTY;
PIN_MAP
'Y'<0>='(AOUT)';
'A'<0>='(AIN)';
'-Y'<0>='(AOUTN)';
'-B'<0>='(AINN)';
END_PIN;
END_MODEL;
END_PRIMITIVE;
END.