16 lines
206 B
Verilog
16 lines
206 B
Verilog
// generated by newgenasym Thu Jan 08 15:59:36 2015
|
|
|
|
|
|
module \10h124 (common, d, y, \y* );
|
|
input common;
|
|
input d;
|
|
output y;
|
|
output \y* ;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|