13 lines
299 B
VHDL
13 lines
299 B
VHDL
-- generated by newgenasym Thu Jan 08 15:59:36 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \10h124\ is
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port (
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COMMON: IN STD_LOGIC;
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D: IN STD_LOGIC;
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Y: OUT STD_LOGIC;
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\y*\: OUT STD_LOGIC);
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end \10h124\;
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