22 lines
609 B
Verilog
22 lines
609 B
Verilog
// generated by chdl_uprev Sat Sep 13 01:37:17 1997
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// Modified to support swift models
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`timescale 1ns/100ps
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module \10h125 (a, \b* , v, y);
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parameter size = 1;
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parameter ModelType = "SWIFT";
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parameter TimingVersion = "MC10H125";
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parameter DelayRange = "max";
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parameter MemoryFile = "memory";
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input [size-1:0] a;
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input [size-1:0] \b* ;
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output [size-1:0] y;
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output v;
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ecl25 #(ModelType, TimingVersion, DelayRange, MemoryFile) inst1[size-1:0] (.AIN(a),
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.AINN(\b* ),
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.AOUT(y) );
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endmodule
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