Tubii_Tk2/Parts/parts/ecl/10h131/entity/verilog.v
2015-02-27 19:09:38 -05:00

20 lines
310 B
Verilog

// generated by newgenasym Wed Oct 01 13:43:16 2014
module \10h131 (clk, d, en, q, \q* , r, s);
parameter size = 1;
input clk;
input [size-1:0] d;
input en;
output [size-1:0] q;
output [size-1:0] \q* ;
input r;
input s;
initial
begin
end
endmodule