20 lines
310 B
Verilog
20 lines
310 B
Verilog
// generated by newgenasym Wed Oct 01 13:43:16 2014
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module \10h131 (clk, d, en, q, \q* , r, s);
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parameter size = 1;
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input clk;
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input [size-1:0] d;
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input en;
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output [size-1:0] q;
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output [size-1:0] \q* ;
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input r;
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input s;
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initial
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begin
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end
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endmodule
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