40 lines
382 B
Verilog
40 lines
382 B
Verilog
// Generated by Part Developer
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// Modified to support swift models
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`timescale 1ns/100ps
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module \10h131 (d,en,q,r,s,clk,\q* );
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parameter size = 1;
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input [size-1:0] d;
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input en;
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output [size-1:0] q;
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input r;
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input s;
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input clk;
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output [size-1:0] \q* ;
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MC10h131 inst1 [size-1:0]
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(
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,
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clk,
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s,
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d,
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en,
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r,
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,
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,
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,
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,
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,
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q,
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\q*
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);
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endmodule
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