Tubii_Tk2/Parts/parts/ecl/el91l/entity/verilog.v
2015-02-27 19:09:38 -05:00

18 lines
253 B
Verilog

// generated by newgenasym Fri May 27 11:15:36 2011
module el91l (in, \in* , out, \out* , vbb, vbb2);
input in;
input \in* ;
output out;
output \out* ;
input vbb;
input vbb2;
initial
begin
end
endmodule