15 lines
361 B
VHDL
15 lines
361 B
VHDL
-- generated by newgenasym Fri May 27 11:15:36 2011
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity EL91L is
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port (
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\in\: IN STD_LOGIC;
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\in*\: IN STD_LOGIC;
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\out\: OUT STD_LOGIC;
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\out*\: OUT STD_LOGIC;
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VBB: IN STD_LOGIC;
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VBB2: IN STD_LOGIC);
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end EL91L;
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