33 lines
632 B
Verilog
33 lines
632 B
Verilog
// generated by newgenasym Tue May 18 12:06:05 2010
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module mc10198 (cext, cs, d, \ecl#20com , \ecl#20ref , \eneg* , \epos* , epwc, hstrig, le,
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\off#20adj , q, \q* , \qr* , reset, \reset* , rext, rs, trig, \trig* );
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input cext;
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inout cs;
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input [7:0] d;
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inout \ecl#20com ;
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inout \ecl#20ref ;
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input \eneg* ;
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input \epos* ;
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input epwc;
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input hstrig;
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input le;
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input \off#20adj ;
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output q;
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output \q* ;
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output \qr* ;
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input reset;
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input \reset* ;
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input rext;
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inout rs;
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input trig;
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input \trig* ;
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initial
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begin
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end
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endmodule
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