29 lines
861 B
VHDL
29 lines
861 B
VHDL
-- generated by newgenasym Tue May 18 12:06:05 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity MC10198 is
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port (
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CEXT: IN STD_LOGIC;
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CS: INOUT STD_LOGIC;
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D: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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\ecl com\: INOUT STD_LOGIC;
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\ecl ref\: INOUT STD_LOGIC;
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\eneg*\: IN STD_LOGIC;
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\epos*\: IN STD_LOGIC;
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EPWC: IN STD_LOGIC;
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HSTRIG: IN STD_LOGIC;
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LE: IN STD_LOGIC;
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\off adj\: IN STD_LOGIC;
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Q: OUT STD_LOGIC;
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\q*\: OUT STD_LOGIC;
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\qr*\: OUT STD_LOGIC;
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RESET: IN STD_LOGIC;
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\reset*\: IN STD_LOGIC;
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REXT: IN STD_LOGIC;
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RS: INOUT STD_LOGIC;
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TRIG: IN STD_LOGIC;
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\trig*\: IN STD_LOGIC);
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end MC10198;
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