31 lines
472 B
Verilog
31 lines
472 B
Verilog
// generated by newgenasym Fri Jul 30 18:03:39 2010
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module \74f245 (a1, a2, a3, a4, a5, a6, a7, a8, b1, b2, b3, b4, b5, b6, b7, b8, dir,
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\oe* );
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input a1;
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input a2;
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input a3;
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input a4;
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input a5;
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input a6;
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input a7;
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input a8;
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output b1;
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output b2;
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output b3;
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output b4;
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output b5;
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output b6;
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output b7;
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output b8;
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input dir;
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input \oe* ;
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initial
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begin
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end
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endmodule
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