27 lines
775 B
VHDL
27 lines
775 B
VHDL
-- generated by newgenasym Fri Jul 30 18:03:39 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74f245\ is
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port (
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A1: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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A5: IN STD_LOGIC;
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A6: IN STD_LOGIC;
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A7: IN STD_LOGIC;
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A8: IN STD_LOGIC;
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B1: OUT STD_LOGIC;
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B2: OUT STD_LOGIC;
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B3: OUT STD_LOGIC;
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B4: OUT STD_LOGIC;
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B5: OUT STD_LOGIC;
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B6: OUT STD_LOGIC;
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B7: OUT STD_LOGIC;
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B8: OUT STD_LOGIC;
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DIR: IN STD_LOGIC;
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\oe*\: IN STD_LOGIC);
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end \74f245\;
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