20 lines
375 B
Verilog
20 lines
375 B
Verilog
/*
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* Created: < wittich 14/08/95>
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* Time-stamp: <95/08/14 14:51:50 wittich>
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* filename: /tape/snopcb/snolib_fec32/testpoint_l/verilog_lib/verilog.v
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*
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* Comments: test point dummy model.
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*
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* Modification History:
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* ------------------------------
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* 14/08/95 Created.
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*
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*/
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module TESTPOINT_L(A) ;
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input A;
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endmodule /* TESTPOINT_L */
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