44 lines
862 B
Verilog
44 lines
862 B
Verilog
// generated by newgenasym Mon Sep 08 19:03:45 2014
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module ad7243 (agnd, bncp, \clr* , cs, d, dcen, dgnd, \ecl#20com , \ecl#20ref , \ldac* ,
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le, \off#20adj , q, \q* , \qr* , refin, refout, reset, \reset* , rofs, rs,
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sclk, sdin, sdo, \sync* , trig, \trig* , vdd, vout, vss);
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input agnd;
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input bncp;
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input \clr* ;
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inout cs;
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input [7:0] d;
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input dcen;
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input dgnd;
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inout \ecl#20com ;
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inout \ecl#20ref ;
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input \ldac* ;
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input le;
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input \off#20adj ;
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output q;
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output \q* ;
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output \qr* ;
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input refin;
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output refout;
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input reset;
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input \reset* ;
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input rofs;
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inout rs;
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input sclk;
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input sdin;
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output sdo;
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input \sync* ;
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input trig;
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input \trig* ;
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input vdd;
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output vout;
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input vss;
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initial
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begin
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end
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endmodule
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