23 lines
377 B
Verilog
23 lines
377 B
Verilog
// generated by newgenasym Mon Jul 11 17:48:15 2011
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module ad7249 (bbarc, \clr* , \ldac* , refin, refout, rofs, sclk, sdin, \sync* ,
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vout);
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input bbarc;
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input \clr* ;
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input \ldac* ;
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input refin;
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output refout;
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output rofs;
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input sclk;
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input sdin;
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input \sync* ;
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output vout;
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initial
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begin
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end
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endmodule
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