Tubii_Tk2/Parts/parts/misc/ad8009/entity/verilog.v
2015-02-27 19:09:38 -05:00

17 lines
244 B
Verilog

// generated by newgenasym Wed Oct 29 14:53:51 2014
module ad8009 (\in+ , \in- , \output , \v+ , \v- );
inout \in+ ;
inout \in- ;
inout \output ;
input \v+ ;
input \v- ;
initial
begin
end
endmodule