18 lines
467 B
VHDL
18 lines
467 B
VHDL
-- generated by newgenasym Wed Oct 22 13:32:12 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ad96685 is
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port (
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GRND1: IN STD_LOGIC;
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GRND2: IN STD_LOGIC;
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INN: IN STD_LOGIC;
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INP: IN STD_LOGIC;
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LTCH: OUT STD_LOGIC;
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QN: OUT STD_LOGIC;
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QP: OUT STD_LOGIC;
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VN: IN STD_LOGIC;
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VP: IN STD_LOGIC);
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end ad96685;
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